1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a cap for a semiconductor device package, and more particularly, to a cap which can form a cavity and plate a via hole having a seed layer, and a manufacturing method thereof.
2. Description of the Related Art
In general, a microstructure package such as an IC, a hybrid chip for communication and an RF MEMS needs a low cost, high yield and ultra small packaging process. Simplification of the packaging process and high reliability is also necessary. Especially, the microstructure package requires a packaging technology allowing the making of a few devices of a single chip, and a via hole filling technology having high stability and reliability.
FIGS. 1 to 3 are cross-sectional views illustrating various methods for plating a via hole of a substrate to manufacture a related art cap for a semiconductor device package.
Referring to FIG. 1, a via hole is formed on a substrate having a thickness below 200 μm, and a metal 2 is filled in the via hole. In a state where a seed layer 3 is formed on the inner circumference of the via hole, the metal 2 is filled to form a fine plating layer. However, the aforementioned structure and method cannot form a cavity such as required in packaging.
As illustrated in FIG. 2, a via hole is formed or a substrate 11 having a thickness below 100 μm at a predetermined depth not to pass through the substrate 11, a seed layer 13 is formed in the via hole, and a metal 12 is filled to form a fine plating layer. As indicated by the dotted line, a cavity 14 may also be formed with a restricted depth.
As shown in FIG. 3, a via hole is formed on a substrate 21 having a thickness over 300 μm, a seed layer 23 is formed on one surface of the substrate 21, and a metal 22 is filled by back contact plating. Since the seed layer 23 is not formed on the inner circumference of the via hole, a fine plating layer is not obtained. That is, in the case where the via hole is plated without the seed layer, alien substances may be trapped on the interface between the silicon (Si) material and the plating material. Therefore, the interface between the Si material and the plating material is weakened to cause defects.
As a result, the aforementioned methods cannot efficiently plate the via hole having the seed layer in the Si wafer which has a thickness over 200 μm and includes a cavity as required in packaging. Moreover, the above methods cannot efficiently perform the processes, including creating the cavity, and thus are not suitable to manufacture a cap for a semiconductor device package.